A semiconductor device such as a memory or a logic requires a reset signal generated in response to power-on in order to initialize a circuit such as a latch at the power-on. Recently, this kind of semiconductor device is sometimes mounted in a sub system apparatus having a so-called hot-swap function of being attachable to and detachable from a main system apparatus in a power-on state. In this case, the reset signal needs to be generated in response to not only power-on but also power-down in order to protect an internal state of the semiconductor device or reset an internal circuit when the sub system apparatus is detached from the main system apparatus.
Generally, a reset circuit which outputs a reset signal in response to power-on and power-down includes a detection circuit detecting a change in power supply voltage and an output circuit outputting the reset signal according to a detection result of the detection circuit. For example, the detection circuit includes a dividing circuit dividing the power supply voltage, a transistor (inverter) receiving a divided voltage at its gate, a load circuit charging a drain node of the transistor, and a buffer circuit outputting a power-on detection signal according to a drain voltage of the transistor. The output circuit includes a latch brining the level of the reset signal into a reset state or a reset release state according to the level of the power-on detection signal (for example, FIG. 2, FIG. 3 of U.S. Patent Publication No. 2005-0275437).
In the above detection circuit, the drain node of the transistor is charged via the load circuit at power-on. By this charge, the power-on detection signal is held in the reset state immediately after the power-on. When the divided voltage exceeds a threshold voltage of the transistor, the transistor is turned on, the level of the drain node is inverted, and the level of the power-on detection signal changes from the reset state to the reset release state.
However, when the power supply voltage increases slowly or the power supply voltage swings at power-on, the dividing circuit sometimes cannot output a normal voltage. In this case, before being fully charged, the drain node changes to a ground voltage by the transistor being turned on. At this time, the level of the power-on detection signal changes to the reset release state after being set to the reset state only for a short time. Alternatively, the level of the power-on detection signal is set to the reset release state without being set to the reset state. As a result, there arises a problem that the circuit such as the latch cannot be reset at power-on. This problem tends to occur when a balance between threshold voltages of a pMOS transistor and an nMOS transistor is lost by a change in semiconductor process. Further, generally, the load circuit is constituted of a pMOS transistor with a small drivability or the like and functions as a high-resistance resistor in many cases. Therefore, if the above transistor functioning as the inverter is slightly turned on, the drain node changes to the ground voltage.
Furthermore, a starter circuit which initializes the detection circuit of the reset circuit at power-on or power-down is sometimes formed in the reset circuit. The starter circuit includes a capacitor to which the power supply voltage is applied. The capacitor always receives the power supply voltage while the system apparatus is operating. Generally, the capacitor may cause a reliability failure due to degradation called TDDB (Time-Dependent Dielectric-Breakdown). The TDDB degradation tends to occur more frequently as the voltage value applied to the capacitor becomes larger and as the application time becomes longer. If the capacitor of the starter circuit degrades due to TDDB and a leak current occurs, the reset circuit becomes unable to detect the power supply voltage. Consequently, a circuit which requires reset at power-on or power-off cannot be reset, which causes the semiconductor device and the system apparatus to malfunction. In other words, there is a possibility that the lives of the semiconductor device and the system apparatus become shorter due to the reliability failure of the capacitor used in the reset circuit.